High-Speed Design Optimization for EMC
Electronic designs containing high speed interfaces often raise EMC concerns. Successful designs require a compromise between functionality and meeting EMC requirements. A straight forward approach is often done by reducing sign rise and fall times. However, it is important to know how far signals can be slewed to ensure proper product functionality over all environmental conditions and component tolerances. At E3 Compliance, we have the tools and experience required to determine the right balance, both analytically and through high accuracy measurements.
Signal Integrity and Timing Analysis
Electronics designers are faced with important challenges to provide robust digital communication interfaces, with higher data rates, while keeping PCB form factors small. Additionally, signal integrity and timing characteristics play an important role in producing reliable products that can also meet EMC requirements. Aggressive timing and limited engineering budgets further complicate the development of final design that meets all requirements.
At E3 Compliance, we have a proven track record of understanding these challenges, and of leveraging our design, analytical and measurement experience to succeed up front in product development. We have observed trends over the years that guide our acquisition and use of state of the art tools and methods. As an example, one such trend is the reduction in allowable timing margins as a function of clock period as shown in the chart below:
To guarantee the proper operation of a given high speed interface, a set of functional requirements corresponding to the relevant technologies needs to be verified both analytically and by accurate measurements. These requirements include signal and system properties such as:
- Setup and Hold time
- Clock High/Low Time
- Clock Jitter
- Rise/Fall times
- Max/Min Voltage (includes xtalk/overshoot)
- Data Eye Mask test
Our systematic approach, and proven simulation and measurement techniques, help our customers save time and money. As part of our services, we design and analyze numerous high speed interfaces, such as:
- Memory (RAM): SDRAM, DDR/DDR2/ DDR3
- Non-Volatile memory: NOR, QSPI, NAND, eMMC
- Display interconnect: RGB, ITU656, MIPI-CSI
- Serial Data: LVDS, MOST, HDMI, USB2, Ethernet, APIX
Measurements play an important role in validating models and confirming design performance to critical requirements. At E3 compliance we use Keysight oscilloscopes, as well as a variety of probes and precision XYZ positioners to probe very small PCB structures without the need for interposers.
Power Integrity Analysis
Good power integrity design ensures higher computational power can be achieved reliably and high speed channels can perform as expected. At E3 Compliance we use both analytical and measurement tools to design and characterize power delivery networks (PDN) and we focus on two requirements:
- Excessive DC voltage drop between the power source and processor pins
- Excessive impedance at presented to processor pins
Poor PDN design can lead to poor signal integrity and EMC issues. That is why we take a proactive approach for screening our customers designs for potential issues and optimizing them prior to artwork release.
Circuit Analysis, Modeling and Design Justification
At E3 Compliance, we have learned over the years that when dealing with volume production, bench-top testing is unlikely to identify all product issues which can lead to field failures. A preferred approach is to use analysis to evaluate performance of the product under worse-case conditions (frequency referred to as Worst-Case Circuit Analysis) – WCCA. The Design Failure Mode & Effects Analysis (DFMEA) is typically used to drive the required calculations, analysis and measurements to secure a product ready design.
WCCA methods can provide an answer to a questions such as “If I consider tolerance stackups, can my part violate a particular requirement?” The methods can also answer a question such as “How often can a violation occur?” (e.g. how many parts per million (PPM) will be outside the specification?).
Many of our customers make use of our design justification documentation to record the analysis and testing done on circuits to prove they are ready for production. They also make use of our analysis plan document that defines what analysis shall be performed and defines a timeline with resources to support its on-time completion.
Contact us today to inquire about our services or engage us to support your needs.